34 lines
1.1 KiB
Plaintext
34 lines
1.1 KiB
Plaintext
DFLL board params node in the board DTS file
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Required properties:
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- sample-rate : control loop sample rate (in Hz)
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- cf : I2C: duration to force the PMIC voltage after frequency change
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- cg : loop gain (signed) - determined during board characterization
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- ci : loop integral gain selector
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- droop-cut-value : control output clock scaler at minimum ring osc freq
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- droop-restore-ramp : clock recovery rate after a voltage droop event
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- scale-out-ramp : voltage output ramp rate
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Optional properties:
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- no-output-forcing : don't force PMIC voltage output during request change
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- fixed-output-forcing : force PMIC voltage during req change for a fixed time
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- auto-output-forcing : force PMIC voltage during req change for a dynamic time
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- cg-scale : if present, divide loop gain by 8 (see 'cg' above)
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Note that one of 'no-output-forcing', 'fixed-output-forcing', or
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'auto-output-forcing' must be specified.
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Example:
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cpu_dfll_board_params {
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sample-rate = <12500>;
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fixed-output-forcing;
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cf = <10>;
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ci = <0>;
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cg = <2>;
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droop-cut-value = <0xf>;
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droop-restore-ramp = <0x0>;
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scale-out-ramp = <0x0>;
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};
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