144 lines
4.7 KiB
Plaintext
144 lines
4.7 KiB
Plaintext
NVIDIA Tegra Power Management Controller (PMC)
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The PMC block interacts with an external Power Management Unit. The PMC
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mostly controls the entry and exit of the system from different sleep
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modes. It provides power-gating controllers for SoC and CPU power-islands.
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Required properties:
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- name : Should be pmc
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- compatible : Should contain "nvidia,tegra<chip>-pmc".
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- reg : Offset and length of the register set for the device
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : Must include the following entries:
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"pclk" (The Tegra clock of that name),
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"clk32k_in" (The 32KHz clock input to Tegra).
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Optional properties:
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- nvidia,invert-interrupt : If present, inverts the PMU interrupt signal.
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The PMU is an external Power Management Unit, whose interrupt output
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signal is fed into the PMC. This signal is optionally inverted, and then
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fed into the ARM GIC. The PMC is not involved in the detection or
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handling of this interrupt signal, merely its inversion.
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- nvidia,suspend-mode : The suspend mode that the platform should use.
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Valid values are 0, 1 and 2:
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0 (LP0): CPU + Core voltage off and DRAM in self-refresh
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1 (LP1): CPU voltage off and DRAM in self-refresh
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2 (LP2): CPU voltage off
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- nvidia,core-power-req-active-high : Boolean, core power request active-high
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- nvidia,sys-clock-req-active-high : Boolean, system clock request active-high
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- nvidia,combined-power-req : Boolean, combined power request for CPU & Core
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- nvidia,cpu-pwr-good-en : Boolean, CPU power good signal (from PMIC to PMC)
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is enabled.
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- nvidia,reset-gpio : GPIO that can be used to warm reset the system.
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Required properties when nvidia,suspend-mode is specified:
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- nvidia,cpu-pwr-good-time : CPU power good time in uS.
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- nvidia,cpu-pwr-off-time : CPU power off time in uS.
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- nvidia,core-pwr-good-time : <Oscillator-stable-time Power-stable-time>
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Core power good time in uS.
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- nvidia,core-pwr-off-time : Core power off time in uS.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,lp0-vec : <start length> Starting address and length of LP0 vector
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The LP0 vector contains the warm boot code that is executed by AVP when
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resuming from the LP0 state. The AVP (Audio-Video Processor) is an ARM7
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processor and always being the first boot processor when chip is power on
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or resume from deep sleep mode. When the system is resumed from the deep
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sleep mode, the warm boot code will restore some PLLs, clocks and then
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bring up CPU0 for resuming the system.
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Example:
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/ SoC dts including file
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pmc@7000f400 {
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compatible = "nvidia,tegra20-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 110>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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nvidia,invert-interrupt;
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nvidia,suspend-mode = <1>;
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nvidia,cpu-pwr-good-time = <2000>;
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nvidia,cpu-pwr-off-time = <100>;
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nvidia,core-pwr-good-time = <3845 3845>;
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nvidia,core-pwr-off-time = <458>;
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nvidia,core-power-req-active-high;
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nvidia,sys-clock-req-active-high;
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nvidia,lp0-vec = <0xbdffd000 0x2000>;
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};
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/ Tegra board dts file
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{
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...
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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clk32k_in: clock {
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compatible = "fixed-clock";
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reg=<0>;
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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};
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...
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};
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Wake up events
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The PMC is the only device that can wake up the system from deep sleep
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mode (i.e. LP0). There are some wake up events that in the PMC wake mask
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register can be used to trigger PMC to wake up the system. The PMC wake
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mask register defines which devices or siganls can be the source to
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trigger PMC waking up. If the devices support waking up system from deep
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sleep mode, then it needs to describe a property for PMC wake up events.
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Here is the property defines the usage.
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Required properties when nvidia,suspend-mode=<0>:
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- nvidia,pmc-wakeup : <pmc_phandle event_type event_offset trigger_type>
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pmc_phandle: the phandle of PMC device tree node
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event_type: 0 = PMC_WAKE_TYPE_GPIO
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1 = PMC_WAKE_TYPE_EVENT
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event_offset: the offset of PMC wake mask register
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trigger_type: set 0 when event_type is PMC_WAKE_TYPE_GPIO
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if event_type is PMC_WAKE_TYPE_EVENT
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0 = PMC_TRIGGER_TYPE_NONE
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1 = PMC_TRIGGER_TYPE_RISING
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2 = PMC_TRIGGER_TYPE_FALLING
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4 = PMC_TRIGGER_TYPE_HIGH
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8 = PMC_TRIGGER_TYPE_LOW
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- #wake-cells : should be 3
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Example:
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/ SoC dts including file
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pmc: pmc {
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compatible = "nvidia,tegra114-pmc";
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reg = <0x7000e400 0x400>;
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clocks = <&tegra_car 261>, <&clk32k_in>;
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clock-names = "pclk", "clk32k_in";
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};
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/ Tegra board dts file
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{
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...
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pmc {
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...
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nvidia,suspend-mode = <0>;
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#wake-cells = <3>;
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...
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};
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...
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pmic {
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...
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nvidia,pmc-wakeup = <&pmc 1 18 8>;
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...
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};
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...
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rtc {
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...
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nvidia,pmc-wakeup = <&pmc 0 16 0>;
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...
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};
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};
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