480 lines
14 KiB
C
480 lines
14 KiB
C
/*
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* Copyright (C) 2011-2013, NVIDIA Corporation
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*
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* Author: Robert Morell <rmorell@nvidia.com>
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* Some code based on fbdev extensions written by:
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* Erik Gilling <konkers@android.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __TEGRA_DC_EXT_H
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#define __TEGRA_DC_EXT_H
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#if defined(__KERNEL__)
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# include <linux/time.h>
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#else
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# include <time.h>
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# include <unistd.h>
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#endif
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/* pixformat - color format */
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#define TEGRA_DC_EXT_FMT_P1 0
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#define TEGRA_DC_EXT_FMT_P2 1
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#define TEGRA_DC_EXT_FMT_P4 2
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#define TEGRA_DC_EXT_FMT_P8 3
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#define TEGRA_DC_EXT_FMT_B4G4R4A4 4
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#define TEGRA_DC_EXT_FMT_B5G5R5A 5
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#define TEGRA_DC_EXT_FMT_B5G6R5 6
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#define TEGRA_DC_EXT_FMT_AB5G5R5 7
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#define TEGRA_DC_EXT_FMT_B8G8R8A8 12
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#define TEGRA_DC_EXT_FMT_R8G8B8A8 13
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#define TEGRA_DC_EXT_FMT_B6x2G6x2R6x2A8 14
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#define TEGRA_DC_EXT_FMT_R6x2G6x2B6x2A8 15
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#define TEGRA_DC_EXT_FMT_YCbCr422 16
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#define TEGRA_DC_EXT_FMT_YUV422 17
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#define TEGRA_DC_EXT_FMT_YCbCr420P 18
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#define TEGRA_DC_EXT_FMT_YUV420P 19
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#define TEGRA_DC_EXT_FMT_YCbCr422P 20
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#define TEGRA_DC_EXT_FMT_YUV422P 21
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#define TEGRA_DC_EXT_FMT_YCbCr422R 22
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#define TEGRA_DC_EXT_FMT_YUV422R 23
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#define TEGRA_DC_EXT_FMT_YCbCr422RA 24
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#define TEGRA_DC_EXT_FMT_YUV422RA 25
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#define TEGRA_DC_EXT_FMT_YCbCr444P 41
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#define TEGRA_DC_EXT_FMT_YUV444P 52
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#define TEGRA_DC_EXT_FMT_YCrCb420SP 42
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#define TEGRA_DC_EXT_FMT_YCbCr420SP 43
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#define TEGRA_DC_EXT_FMT_YCrCb422SP 44
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#define TEGRA_DC_EXT_FMT_YCbCr422SP 45
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#define TEGRA_DC_EXT_FMT_YVU420SP 53
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#define TEGRA_DC_EXT_FMT_YUV420SP 54
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#define TEGRA_DC_EXT_FMT_YVU422SP 55
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#define TEGRA_DC_EXT_FMT_YUV422SP 56
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#define TEGRA_DC_EXT_FMT_YVU444SP 59
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#define TEGRA_DC_EXT_FMT_YUV444SP 60
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/* color format type field is 8-bits */
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#define TEGRA_DC_EXT_FMT_SHIFT 0
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#define TEGRA_DC_EXT_FMT_MASK (0xff << TEGRA_DC_EXT_FMT_SHIFT)
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/* pixformat - byte order options ( w x y z ) */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_NOSWAP (0 << 8) /* ( 3 2 1 0 ) */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_SWAP2 (1 << 8) /* ( 2 3 0 1 ) */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_SWAP4 (2 << 8) /* ( 0 1 2 3 ) */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_SWAP4HW (3 << 8) /* ( 1 0 3 2 ) */
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/* the next two are not available on T30 or earlier */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_SWAP02 (4 << 8) /* ( 3 0 1 2 ) */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_SWAPLEFT (5 << 8) /* ( 2 1 0 3 ) */
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/* byte order field is 4-bits */
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#define TEGRA_DC_EXT_FMT_BYTEORDER_SHIFT 8
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#define TEGRA_DC_EXT_FMT_BYTEORDER_MASK \
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(0x0f << TEGRA_DC_EXT_FMT_BYTEORDER_SHIFT)
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#define TEGRA_DC_EXT_BLEND_NONE 0
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#define TEGRA_DC_EXT_BLEND_PREMULT 1
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#define TEGRA_DC_EXT_BLEND_COVERAGE 2
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#define TEGRA_DC_EXT_FLIP_FLAG_INVERT_H (1 << 0)
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#define TEGRA_DC_EXT_FLIP_FLAG_INVERT_V (1 << 1)
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#define TEGRA_DC_EXT_FLIP_FLAG_TILED (1 << 2)
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#define TEGRA_DC_EXT_FLIP_FLAG_CURSOR (1 << 3)
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#define TEGRA_DC_EXT_FLIP_FLAG_GLOBAL_ALPHA (1 << 4)
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#define TEGRA_DC_EXT_FLIP_FLAG_BLOCKLINEAR (1 << 5)
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#define TEGRA_DC_EXT_FLIP_FLAG_SCAN_COLUMN (1 << 6)
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#define TEGRA_DC_EXT_FLIP_FLAG_INTERLACE (1 << 7)
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struct tegra_dc_ext_flip_windowattr {
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__s32 index;
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__u32 buff_id;
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__u32 blend;
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__u32 offset;
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__u32 offset_u;
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__u32 offset_v;
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__u32 stride;
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__u32 stride_uv;
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__u32 pixformat;
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/*
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* x, y, w, h are fixed-point: 20 bits of integer (MSB) and 12 bits of
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* fractional (LSB)
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*/
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__u32 x;
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__u32 y;
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__u32 w;
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__u32 h;
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__u32 out_x;
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__u32 out_y;
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__u32 out_w;
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__u32 out_h;
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__u32 z;
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__u32 swap_interval;
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struct timespec timestamp;
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__u32 pre_syncpt_id;
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__u32 pre_syncpt_val;
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/* These two are optional; if zero, U and V are taken from buff_id */
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__u32 buff_id_u;
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__u32 buff_id_v;
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__u32 flags;
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__u8 global_alpha; /* requires TEGRA_DC_EXT_FLIP_FLAG_GLOBAL_ALPHA */
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/* log2(blockheight) for blocklinear format */
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__u8 block_height_log2;
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__u8 pad1[2];
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__u32 offset2;
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__u32 offset_u2;
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__u32 offset_v2;
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/* Leave some wiggle room for future expansion */
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__u32 pad2[1];
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};
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#define TEGRA_DC_EXT_FLIP_N_WINDOWS 3
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struct tegra_dc_ext_flip {
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struct tegra_dc_ext_flip_windowattr win[TEGRA_DC_EXT_FLIP_N_WINDOWS];
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__u32 post_syncpt_id;
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__u32 post_syncpt_val;
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};
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struct tegra_dc_ext_flip_2 {
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struct tegra_dc_ext_flip_windowattr *win;
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__u8 win_num;
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__u8 reserved1; /* unused - must be 0 */
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__u16 reserved2; /* unused - must be 0 */
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__u32 post_syncpt_id;
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__u32 post_syncpt_val;
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__u16 dirty_rect[4]; /* x,y,w,h for partial screen update. 0 ignores */
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};
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/*
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* Cursor image format:
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*
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* Tegra hardware supports two different cursor formats:
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*
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* (1) Two color cursor: foreground and background colors are
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* specified by the client in RGB8.
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*
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* The two-color image should be specified as two 1bpp bitmaps
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* immediately following each other in memory. Each pixel in the
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* final cursor will be constructed from the bitmaps with the
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* following logic:
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*
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* bitmap1 bitmap0
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* (mask) (color)
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* 1 0 transparent
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* 1 1 inverted
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* 0 0 background color
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* 0 1 foreground color
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*
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* This format is supported when TEGRA_DC_EXT_CONTROL_GET_CAPABILITIES
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* reports the TEGRA_DC_EXT_CAPABILITIES_CURSOR_TWO_COLOR bit.
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*
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* (2) RGBA cursor: in this case the image is four bytes per pixel,
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* with alpha in the low eight bits.
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*
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* The RGB components of the cursor image can be either
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* premultipled by alpha:
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*
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* cursor[r,g,b] + desktop[r,g,b] * (1 - cursor[a])
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*
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* or not:
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*
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* cursor[r,g,b] * cursor[a] + desktop[r,g,b] * (1 - cursor[a])
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*
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* TEGRA_DC_EXT_CONTROL_GET_CAPABILITIES will report one or more of
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* TEGRA_DC_EXT_CURSOR_FLAGS_RGBA{,_NON}_PREMULT_ALPHA to indicate
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* which are supported on the current hardware.
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*
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* Specify one of TEGRA_DC_EXT_CURSOR_FLAGS to indicate the format.
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*
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* Exactly one of the SIZE flags must be specified.
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*/
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#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_32x32 ((1 & 0x7) << 0)
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#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_64x64 ((2 & 0x7) << 0)
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#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_128x128 ((3 & 0x7) << 0)
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#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE_256x256 ((4 & 0x7) << 0)
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#define TEGRA_DC_EXT_CURSOR_IMAGE_FLAGS_SIZE(x) (((x) & 0x7) >> 0)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_2BIT_LEGACY (0)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_RGBA_NON_PREMULT_ALPHA (1)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_RGBA_PREMULT_ALPHA (3)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_FLAGS_2BIT_LEGACY \
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(TEGRA_DC_EXT_CURSOR_FORMAT_2BIT_LEGACY << 16)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_FLAGS_RGBA_NON_PREMULT_ALPHA \
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(TEGRA_DC_EXT_CURSOR_FORMAT_RGBA_NON_PREMULT_ALPHA << 16)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_FLAGS_RGBA_PREMULT_ALPHA \
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(TEGRA_DC_EXT_CURSOR_FORMAT_RGBA_PREMULT_ALPHA << 16)
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#define TEGRA_DC_EXT_CURSOR_FORMAT_FLAGS(x) (((x) >> 16) & 0x7)
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/* aliases for source-level backwards compatibility */
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#define TEGRA_DC_EXT_CURSOR_FLAGS_RGBA_NORMAL \
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TEGRA_DC_EXT_CURSOR_FORMAT_FLAGS_RGBA_NON_PREMULT_ALPHA
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#define TEGRA_DC_EXT_CURSOR_FLAGS_2BIT_LEGACY \
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TEGRA_DC_EXT_CURSOR_FORMAT_FLAGS_2BIT_LEGACY
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enum CR_MODE {
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legacy,
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normal,
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};
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struct tegra_dc_ext_cursor_image {
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struct {
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__u8 r;
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__u8 g;
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__u8 b;
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} foreground, background;
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__u32 buff_id;
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__u32 flags;
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__s16 x;
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__s16 y;
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__u32 vis;
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enum CR_MODE mode;
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};
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/* Possible flags for struct nvdc_cursor's flags field */
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#define TEGRA_DC_EXT_CURSOR_FLAGS_VISIBLE (1 << 0)
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struct tegra_dc_ext_cursor {
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__s16 x;
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__s16 y;
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__u32 flags;
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};
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/*
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* Color conversion is performed as follows:
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*
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* r = sat(kyrgb * sat(y + yof) + kur * u + kvr * v)
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* g = sat(kyrgb * sat(y + yof) + kug * u + kvg * v)
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* b = sat(kyrgb * sat(y + yof) + kub * u + kvb * v)
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*
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* Coefficients should be specified as fixed-point values; the exact format
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* varies for each coefficient.
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* The format for each coefficient is listed below with the syntax:
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* - A "s." prefix means that the coefficient has a sign bit (twos complement).
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* - The first number is the number of bits in the integer component (not
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* including the optional sign bit).
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* - The second number is the number of bits in the fractional component.
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*
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* All three fields should be tightly packed, justified to the LSB of the
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* 16-bit value. For example, the "s.2.8" value should be packed as:
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* (MSB) 5 bits of 0, 1 bit of sign, 2 bits of integer, 8 bits of frac (LSB)
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*/
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struct tegra_dc_ext_csc {
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__u32 win_index;
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__u16 yof; /* s.7.0 */
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__u16 kyrgb; /* 2.8 */
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__u16 kur; /* s.2.8 */
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__u16 kvr; /* s.2.8 */
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__u16 kug; /* s.1.8 */
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__u16 kvg; /* s.1.8 */
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__u16 kub; /* s.2.8 */
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__u16 kvb; /* s.2.8 */
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};
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struct tegra_dc_ext_cmu {
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__u16 cmu_enable;
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__u16 csc[9];
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__u16 lut1[256];
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__u16 lut2[960];
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};
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/*
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* RGB Lookup table
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*
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* In true-color and YUV modes this is used for post-CSC RGB->RGB lookup, i.e.
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* gamma-correction. In palette-indexed RGB modes, this table designates the
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* mode's color palette.
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*
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* To convert 8-bit per channel RGB values to 16-bit, duplicate the 8 bits
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* in low and high byte, e.g. r=r|(r<<8)
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*
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* To just update flags, set len to 0.
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*
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* Current Tegra DC hardware supports 8-bit per channel to 8-bit per channel,
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* and each hardware window (overlay) uses its own lookup table.
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*
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*/
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struct tegra_dc_ext_lut {
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__u32 win_index; /* window index to set lut for */
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__u32 flags; /* Flag bitmask, see TEGRA_DC_EXT_LUT_FLAGS_* */
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__u32 start; /* start index to update lut from */
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__u32 len; /* number of valid lut entries */
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__u16 *r; /* array of 16-bit red values, 0 to reset */
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__u16 *g; /* array of 16-bit green values, 0 to reset */
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__u16 *b; /* array of 16-bit blue values, 0 to reset */
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};
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/* tegra_dc_ext_lut.flags - override global fb device lookup table.
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* Default behaviour is double-lookup.
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*/
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#define TEGRA_DC_EXT_LUT_FLAGS_FBOVERRIDE 0x01
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#define TEGRA_DC_EXT_FLAGS_ENABLED 1
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struct tegra_dc_ext_status {
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__u32 flags;
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/* Leave some wiggle room for future expansion */
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__u32 pad[3];
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};
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struct tegra_dc_ext_feature {
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__u32 length;
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__u32 *entries;
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};
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#define TEGRA_DC_EXT_SET_NVMAP_FD \
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_IOW('D', 0x00, __s32)
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#define TEGRA_DC_EXT_GET_WINDOW \
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_IOW('D', 0x01, __u32)
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#define TEGRA_DC_EXT_PUT_WINDOW \
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_IOW('D', 0x02, __u32)
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#define TEGRA_DC_EXT_FLIP \
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_IOWR('D', 0x03, struct tegra_dc_ext_flip)
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#define TEGRA_DC_EXT_GET_CURSOR \
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_IO('D', 0x04)
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#define TEGRA_DC_EXT_PUT_CURSOR \
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_IO('D', 0x05)
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#define TEGRA_DC_EXT_SET_CURSOR_IMAGE \
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_IOW('D', 0x06, struct tegra_dc_ext_cursor_image)
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#define TEGRA_DC_EXT_SET_CURSOR \
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_IOW('D', 0x07, struct tegra_dc_ext_cursor)
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#define TEGRA_DC_EXT_SET_CSC \
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_IOW('D', 0x08, struct tegra_dc_ext_csc)
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#define TEGRA_DC_EXT_GET_STATUS \
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_IOR('D', 0x09, struct tegra_dc_ext_status)
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/*
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* Returns the auto-incrementing vblank syncpoint for the head associated with
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* this device node
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*/
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#define TEGRA_DC_EXT_GET_VBLANK_SYNCPT \
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_IOR('D', 0x09, __u32)
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#define TEGRA_DC_EXT_SET_LUT \
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_IOW('D', 0x0A, struct tegra_dc_ext_lut)
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#define TEGRA_DC_EXT_GET_FEATURES \
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_IOW('D', 0x0B, struct tegra_dc_ext_feature)
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#define TEGRA_DC_EXT_CURSOR_CLIP \
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_IOW('D', 0x0C, __s32)
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#define TEGRA_DC_EXT_SET_CMU \
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_IOW('D', 0x0D, struct tegra_dc_ext_cmu)
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#define TEGRA_DC_EXT_FLIP2 \
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_IOWR('D', 0x0E, struct tegra_dc_ext_flip_2)
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#define TEGRA_DC_EXT_GET_CMU \
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_IOR('D', 0x0F, struct tegra_dc_ext_cmu)
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#define TEGRA_DC_EXT_GET_CUSTOM_CMU \
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_IOR('D', 0x10, struct tegra_dc_ext_cmu)
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#define TEGRA_DC_EXT_SET_CURSOR_IMAGE_LOW_LATENCY \
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_IOW('D', 0x11, struct tegra_dc_ext_cursor_image)
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#define TEGRA_DC_EXT_SET_CURSOR_LOW_LATENCY \
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_IOW('D', 0x12, struct tegra_dc_ext_cursor_image)
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enum tegra_dc_ext_control_output_type {
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TEGRA_DC_EXT_DSI,
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TEGRA_DC_EXT_LVDS,
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TEGRA_DC_EXT_VGA,
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TEGRA_DC_EXT_HDMI,
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TEGRA_DC_EXT_DVI,
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TEGRA_DC_EXT_DP,
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};
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/*
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* Get the properties for a given output.
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*
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* handle (in): Which output to query
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* type (out): Describes the type of the output
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* connected (out): Non-zero iff the output is currently connected
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* associated_head (out): The head number that the output is currently
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* bound to. -1 iff the output is not associated with any head.
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* head_mask (out): Bitmask of which heads the output may be bound to (some
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* outputs are permanently bound to a single head).
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*/
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struct tegra_dc_ext_control_output_properties {
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__u32 handle;
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enum tegra_dc_ext_control_output_type type;
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__u32 connected;
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__s32 associated_head;
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__u32 head_mask;
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};
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/*
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* This allows userspace to query the raw EDID data for the specified output
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* handle.
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*
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* Here, the size parameter is both an input and an output:
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* 1. Userspace passes in the size of the buffer allocated for data.
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* 2. If size is too small, the call fails with the error EFBIG; otherwise, the
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* raw EDID data is written to the buffer pointed to by data. In both
|
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* cases, size will be filled in with the size of the data.
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*/
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struct tegra_dc_ext_control_output_edid {
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__u32 handle;
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__u32 size;
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void *data;
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};
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|
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struct tegra_dc_ext_event {
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__u32 type;
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ssize_t data_size;
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char data[0];
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};
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#define TEGRA_DC_EXT_EVENT_HOTPLUG 0x1
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struct tegra_dc_ext_control_event_hotplug {
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|
__u32 handle;
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|
};
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|
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#define TEGRA_DC_EXT_EVENT_BANDWIDTH 0x2
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struct tegra_dc_ext_control_event_bandwidth {
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|
__u32 handle;
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|
};
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|
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#define TEGRA_DC_EXT_CAPABILITIES_CURSOR_MODE (1 << 0)
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#define TEGRA_DC_EXT_CAPABILITIES_BLOCKLINEAR (1 << 1)
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|
|
|
#define TEGRA_DC_EXT_CAPABILITIES_CURSOR_TWO_COLOR (1 << 2)
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#define TEGRA_DC_EXT_CAPABILITIES_CURSOR_RGBA_NON_PREMULT_ALPHA (1 << 3)
|
|
#define TEGRA_DC_EXT_CAPABILITIES_CURSOR_RGBA_PREMULT_ALPHA (1 << 4)
|
|
|
|
struct tegra_dc_ext_control_capabilities {
|
|
__u32 caps;
|
|
/* Leave some wiggle room for future expansion */
|
|
__u32 pad[3];
|
|
};
|
|
|
|
#define TEGRA_DC_EXT_CONTROL_GET_NUM_OUTPUTS \
|
|
_IOR('C', 0x00, __u32)
|
|
#define TEGRA_DC_EXT_CONTROL_GET_OUTPUT_PROPERTIES \
|
|
_IOWR('C', 0x01, struct tegra_dc_ext_control_output_properties)
|
|
#define TEGRA_DC_EXT_CONTROL_GET_OUTPUT_EDID \
|
|
_IOWR('C', 0x02, struct tegra_dc_ext_control_output_edid)
|
|
#define TEGRA_DC_EXT_CONTROL_SET_EVENT_MASK \
|
|
_IOW('C', 0x03, __u32)
|
|
#define TEGRA_DC_EXT_CONTROL_GET_CAPABILITIES \
|
|
_IOR('C', 0x04, struct tegra_dc_ext_control_capabilities)
|
|
|
|
#endif /* __TEGRA_DC_EXT_H */
|