174 lines
6.3 KiB
C
174 lines
6.3 KiB
C
/*
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* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _TEGRA_USB_PMC_INTERFACE_H_
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#define _TEGRA_USB_PMC_INTERFACE_H_
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#define UHSIC_INST(inst, x, y) ((inst == 1) ? x : y)
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#define PMC_UHSIC_SLEEP_CFG(inst) UHSIC_INST(inst, 0x1fc, 0x284)
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#define UHSIC_MASTER_ENABLE(inst) (1 << UHSIC_INST(inst, 24, 0))
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#define UHSIC_WAKE_VAL(inst, x) (((x) & 0xf) << UHSIC_INST(inst, 28, 4))
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#define WAKE_VAL_SD10 0x2
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#define UTMIP_PMC_WAKEUP0 0x84c
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#define UHSIC_PMC_WAKEUP0 0xc34
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#define EVENT_INT_ENB (1 << 0)
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#define PMC_UHSIC_TRIGGERS(inst) UHSIC_INST(inst, 0x1ec, 0x27c)
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#define UHSIC_CLR_WALK_PTR(inst) (1 << UHSIC_INST(inst, 3, 0))
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#define UHSIC_CLR_WAKE_ALARM(inst) (1 << UHSIC_INST(inst, 15, 3))
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#define PMC_UHSIC_SLEEPWALK_CFG(inst) UHSIC_INST(inst, 0x200, 0x288)
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#define UHSIC_LINEVAL_WALK_EN(inst) (1 << UHSIC_INST(inst, 31, 7))
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#define PMC_UHSIC_MASTER_CONFIG(inst) UHSIC_INST(inst, 0x274, 0x29c)
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#define UHSIC_PWR(inst) (1 << UHSIC_INST(inst, 3, 0))
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#define PMC_UHSIC_FAKE(inst) UHSIC_INST(inst, 0x218, 0x294)
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#define UHSIC_FAKE_STROBE_VAL(inst) (1 << UHSIC_INST(inst, 12, 0))
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#define UHSIC_FAKE_DATA_VAL(inst) (1 << UHSIC_INST(inst, 13, 1))
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#define PMC_SLEEPWALK_UHSIC(inst) UHSIC_INST(inst, 0x210, 0x28c)
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#define UHSIC_STROBE_RPD_A (1 << 0)
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#define UHSIC_DATA_RPD_A (1 << 1)
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#define UHSIC_STROBE_RPU_A (1 << 2)
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#define UHSIC_DATA_RPU_A (1 << 3)
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#define UHSIC_STROBE_RPD_B (1 << 8)
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#define UHSIC_DATA_RPD_B (1 << 9)
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#define UHSIC_STROBE_RPU_B (1 << 10)
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#define UHSIC_DATA_RPU_B (1 << 11)
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#define UHSIC_STROBE_RPD_C (1 << 16)
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#define UHSIC_DATA_RPD_C (1 << 17)
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#define UHSIC_STROBE_RPU_C (1 << 18)
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#define UHSIC_DATA_RPU_C (1 << 19)
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#define UHSIC_STROBE_RPD_D (1 << 24)
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#define UHSIC_DATA_RPD_D (1 << 25)
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#define UHSIC_STROBE_RPU_D (1 << 26)
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#define UHSIC_DATA_RPU_D (1 << 27)
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#define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 20)
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#define PMC_USB_DEBOUNCE 0xec
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#define UTMIP_LINE_DEB_CNT(x) (((x) & 0xf) << 16)
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#define PMC_USB_DEBOUNCE_VAL(x) ((x) & 0xffff)
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#define PMC_USB_AO 0xf0
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#define HSIC_RESERVED(inst) (3 << UHSIC_INST(inst, 14, 18))
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#define STROBE_VAL_PD(inst) (1 << UHSIC_INST(inst, 12, 16))
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#define DATA_VAL_PD(inst) (1 << UHSIC_INST(inst, 13, 17))
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#define PMC_POWER_DOWN_MASK 0xffff
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#define USB_ID_PD(inst) (1 << ((4 * (inst)) + 3))
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#define VBUS_WAKEUP_PD(inst) (1 << ((4 * (inst)) + 2))
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#define USBON_VAL_PD(inst) (1 << ((4 * (inst)) + 1))
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#define USBON_VAL_PD_P2 (1 << 9)
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#define USBON_VAL_PD_P1 (1 << 5)
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#define USBON_VAL_PD_P0 (1 << 1)
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#define USBOP_VAL_PD(inst) (1 << (4 * (inst)))
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#define USBOP_VAL_PD_P2 (1 << 8)
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#define USBOP_VAL_PD_P1 (1 << 4)
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#define USBOP_VAL_PD_P0 (1 << 0)
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#define PMC_USB_AO_PD_P2 (0xf << 8)
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#define PMC_USB_AO_ID_PD_P0 (1 << 3)
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#define PMC_USB_AO_VBUS_WAKEUP_PD_P0 (1 << 2)
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#define PMC_TRIGGERS 0x1ec
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#define UTMIP_CLR_WALK_PTR(inst) (1 << (inst))
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#define UTMIP_CLR_WALK_PTR_P2 (1 << 2)
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#define UTMIP_CLR_WALK_PTR_P1 (1 << 1)
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#define UTMIP_CLR_WALK_PTR_P0 (1 << 0)
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#define UTMIP_CAP_CFG(inst) (1 << ((inst) + 4))
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#define UTMIP_CAP_CFG_P2 (1 << 6)
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#define UTMIP_CAP_CFG_P1 (1 << 5)
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#define UTMIP_CAP_CFG_P0 (1 << 4)
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#define UTMIP_CLR_WAKE_ALARM(inst) (1 << ((inst) + 12))
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#define UTMIP_CLR_WAKE_ALARM_P2 (1 << 14)
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#define PMC_PAD_CFG 0x1f4
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#define PMC_UTMIP_TERM_PAD_CFG 0x1f8
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#define PMC_TCTRL_VAL(x) (((x) & 0x1f) << 5)
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#define PMC_RCTRL_VAL(x) (((x) & 0x1f) << 0)
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#define PMC_SLEEP_CFG 0x1fc
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#define UTMIP_TCTRL_USE_PMC(inst) (1 << ((8 * (inst)) + 3))
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#define UTMIP_TCTRL_USE_PMC_P2 (1 << 19)
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#define UTMIP_TCTRL_USE_PMC_P1 (1 << 11)
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#define UTMIP_TCTRL_USE_PMC_P0 (1 << 3)
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#define UTMIP_RCTRL_USE_PMC(inst) (1 << ((8 * (inst)) + 2))
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#define UTMIP_RCTRL_USE_PMC_P2 (1 << 18)
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#define UTMIP_RCTRL_USE_PMC_P1 (1 << 10)
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#define UTMIP_RCTRL_USE_PMC_P0 (1 << 2)
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#define UTMIP_FSLS_USE_PMC(inst) (1 << ((8 * (inst)) + 1))
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#define UTMIP_FSLS_USE_PMC_P2 (1 << 17)
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#define UTMIP_FSLS_USE_PMC_P1 (1 << 9)
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#define UTMIP_FSLS_USE_PMC_P0 (1 << 1)
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#define UTMIP_MASTER_ENABLE(inst) (1 << (8 * (inst)))
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#define UTMIP_MASTER_ENABLE_P2 (1 << 16)
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#define UTMIP_MASTER_ENABLE_P1 (1 << 8)
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#define UTMIP_MASTER_ENABLE_P0 (1 << 0)
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#define PMC_SLEEPWALK_CFG 0x200
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#define UTMIP_LINEVAL_WALK_EN(inst) (1 << ((8 * (inst)) + 7))
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#define UTMIP_LINEVAL_WALK_EN_P2 (1 << 23)
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#define UTMIP_LINEVAL_WALK_EN_P1 (1 << 15)
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#define UTMIP_LINEVAL_WALK_EN_P0 (1 << 7)
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#define UTMIP_WAKE_VAL(inst, x) (((x) & 0xf) << ((8 * (inst)) + 4))
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#define UTMIP_WAKE_VAL_P2(x) (((x) & 0xf) << 20)
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#define UTMIP_WAKE_VAL_P1(x) (((x) & 0xf) << 12)
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#define UTMIP_WAKE_VAL_P0(x) (((x) & 0xf) << 4)
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#define WAKE_VAL_NONE 0xc
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#define WAKE_VAL_ANY 0xF
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#define WAKE_VAL_FSJ 0x2
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#define WAKE_VAL_FSK 0x1
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#define WAKE_VAL_SE0 0x0
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#define PMC_SLEEPWALK_REG(inst) (0x204 + (4 * (inst)))
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#define UTMIP_USBOP_RPD_A (1 << 0)
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#define UTMIP_USBON_RPD_A (1 << 1)
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#define UTMIP_AP_A (1 << 4)
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#define UTMIP_AN_A (1 << 5)
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#define UTMIP_HIGHZ_A (1 << 6)
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#define UTMIP_USBOP_RPD_B (1 << 8)
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#define UTMIP_USBON_RPD_B (1 << 9)
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#define UTMIP_AP_B (1 << 12)
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#define UTMIP_AN_B (1 << 13)
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#define UTMIP_HIGHZ_B (1 << 14)
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#define UTMIP_USBOP_RPD_C (1 << 16)
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#define UTMIP_USBON_RPD_C (1 << 17)
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#define UTMIP_AP_C (1 << 20)
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#define UTMIP_AN_C (1 << 21)
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#define UTMIP_HIGHZ_C (1 << 22)
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#define UTMIP_USBOP_RPD_D (1 << 24)
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#define UTMIP_USBON_RPD_D (1 << 25)
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#define UTMIP_AP_D (1 << 28)
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#define UTMIP_AN_D (1 << 29)
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#define UTMIP_HIGHZ_D (1 << 30)
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#define PMC_UTMIP_FAKE 0x218
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#define USBON_VAL(inst) (1 << ((4 * (inst)) + 1))
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#define USBON_VAL_P2 (1 << 9)
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#define USBON_VAL_P1 (1 << 5)
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#define USBON_VAL_P0 (1 << 1)
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#define USBOP_VAL(inst) (1 << (4 * (inst)))
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#define USBOP_VAL_P2 (1 << 8)
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#define USBOP_VAL_P1 (1 << 4)
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#define USBOP_VAL_P0 (1 << 0)
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#define PMC_UTMIP_BIAS_MASTER_CNTRL 0x270
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#define BIAS_MASTER_PROG_VAL (1 << 1)
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#define PMC_UTMIP_MASTER_CONFIG 0x274
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#define UTMIP_PWR(inst) (1 << (inst))
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#endif /* _TEGRA_USB_PMC_INTERFACE_H_ */
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