182 lines
5.0 KiB
C
182 lines
5.0 KiB
C
/*
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* Copyright (c) 2010 Google, Inc
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef _MACH_TEGRA_POWERGATE_H_
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#define _MACH_TEGRA_POWERGATE_H_
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struct clk;
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#define TEGRA_POWERGATE_CPU 0
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#define TEGRA_POWERGATE_3D 1
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#define TEGRA_POWERGATE_VENC 2
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#define TEGRA_POWERGATE_PCIE 3
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#define TEGRA_POWERGATE_VDEC 4
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#define TEGRA_POWERGATE_L2 5
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#define TEGRA_POWERGATE_MPE 6
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#define TEGRA_POWERGATE_HEG 7
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#define TEGRA_POWERGATE_SATA 8
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#define TEGRA_POWERGATE_CPU1 9
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#define TEGRA_POWERGATE_CPU2 10
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#define TEGRA_POWERGATE_CPU3 11
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#define TEGRA_POWERGATE_CELP 12
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#define TEGRA_POWERGATE_3D1 13
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#define TEGRA_POWERGATE_CPU0 14
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#define TEGRA_POWERGATE_C0NC 15
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#define TEGRA_POWERGATE_C1NC 16
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#define TEGRA_POWERGATE_SOR 17
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#define TEGRA_POWERGATE_DIS 18
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#define TEGRA_POWERGATE_DISB 19
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#define TEGRA_POWERGATE_XUSBA 20
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#define TEGRA_POWERGATE_XUSBB 21
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#define TEGRA_POWERGATE_XUSBC 22
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#define TEGRA_POWERGATE_VIC 23
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#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
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#define MAX_CLK_EN_NUM 9
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/**
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* struct partition_clk_info - clock infomation needed by power partition
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*
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* @clk_name: name of the clock
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* @clk_ptr: pointer to the clock
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*/
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struct partition_clk_info {
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const char *clk_name;
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struct clk *clk_ptr;
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};
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/**
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* struct powergate_partition_info - power partition information
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*
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* @name: name of the power domain
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* @clk_info: clock information needed by the power partition
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*/
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struct powergate_partition_info {
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const char *name;
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struct partition_clk_info clk_info[MAX_CLK_EN_NUM];
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};
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/**
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* struct powergate_ops - callback of SoC specific power operations
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*
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* get_powergate_lock: retrieve the lock for power partition control
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* get_powergate_domain_name: get the domain name
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* powergate_partition: shut off parition , only needed by Tegra114 or later
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* unpowergate_partition: power on partition, only needed by Tegra114 or later
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*/
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struct powergate_ops {
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const char *(*get_powergate_domain_name)(int id);
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int (*powergate_partition)(int id);
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int (*unpowergate_partition)(int id);
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};
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/**
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* struct powergate - SoC powergate manager
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*
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* @soc_name: name of the SoC
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* @num_powerdomains: number of power domains supported in this SoC
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* @num_cpu_domains: number of cpu domains supported in this SoC
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* @cpu_domain_map: map from the physical cpu to the cpu domain id
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* @ops: SoC specific operations for power domain
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*/
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struct powergate {
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const char *soc_name;
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int num_powerdomains;
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int num_cpu_domains;
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const u8 *cpu_domain_map;
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struct powergate_ops *ops;
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};
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#define TEGRA_IO_RAIL_CSIA 0
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#define TEGRA_IO_RAIL_CSIB 1
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#define TEGRA_IO_RAIL_DSI 2
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#define TEGRA_IO_RAIL_MIPI_BIAS 3
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#define TEGRA_IO_RAIL_PEX_BIAS 4
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#define TEGRA_IO_RAIL_PEX_CLK1 5
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#define TEGRA_IO_RAIL_PEX_CLK2 6
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#define TEGRA_IO_RAIL_USB0 9
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#define TEGRA_IO_RAIL_USB1 10
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#define TEGRA_IO_RAIL_USB2 11
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#define TEGRA_IO_RAIL_USB_BIAS 12
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#define TEGRA_IO_RAIL_NAND 13
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#define TEGRA_IO_RAIL_UART 14
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#define TEGRA_IO_RAIL_BB 15
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#define TEGRA_IO_RAIL_AUDIO 17
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#define TEGRA_IO_RAIL_HSIC 19
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#define TEGRA_IO_RAIL_COMP 22
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#define TEGRA_IO_RAIL_HDMI 28
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#define TEGRA_IO_RAIL_PEX_CNTRL 32
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#define TEGRA_IO_RAIL_SDMMC1 33
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#define TEGRA_IO_RAIL_SDMMC3 34
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#define TEGRA_IO_RAIL_SDMMC4 35
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#define TEGRA_IO_RAIL_CAM 36
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#define TEGRA_IO_RAIL_RES 37
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#define TEGRA_IO_RAIL_HV 38
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#define TEGRA_IO_RAIL_DSIB 39
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#define TEGRA_IO_RAIL_DSIC 40
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#define TEGRA_IO_RAIL_DSID 41
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#define TEGRA_IO_RAIL_CSIE 44
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#define TEGRA_IO_RAIL_LVDS 57
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#define TEGRA_IO_RAIL_SYS_DDC 58
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int tegra_powergate_is_powered(int id);
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int tegra_powergate_power_on(int id);
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int tegra_powergate_power_off(int id);
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int tegra_powergate_remove_clamping(int id);
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/* Must be called with clk disabled, and returns with clk enabled */
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int tegra_powergate_sequence_power_up(int id, struct clk *clk);
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int tegra_powergate_partition(int id);
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int tegra_unpowergate_partition(int id);
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC
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struct powergate * __init tegra20_powergate_init(void);
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#else
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static inline struct powergate * __init tegra20_powergate_init(void)
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{ return NULL; }
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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struct powergate * __init tegra30_powergate_init(void);
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#else
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static inline struct powergate * __init tegra30_powergate_init(void)
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{ return NULL; }
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#endif
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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struct powergate * __init tegra114_powergate_init(void);
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#else
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static inline struct powergate * __init tegra114_powergate_init(void)
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{ return NULL; }
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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struct powergate * __init tegra124_powergate_init(void);
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#else
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static inline struct powergate * __init tegra124_powergate_init(void)
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{ return NULL; }
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#endif
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int tegra_io_rail_power_on(int id);
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int tegra_io_rail_power_off(int id);
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#endif /* _MACH_TEGRA_POWERGATE_H_ */
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