150 lines
5.0 KiB
C
150 lines
5.0 KiB
C
/*
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* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __LINUX_NVHOST_DBG_GPU_IOCTL_H
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#define __LINUX_NVHOST_DBG_GPU_IOCTL_H
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#include <linux/ioctl.h>
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#include <linux/types.h>
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#if !defined(__KERNEL__)
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#define __user
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#endif
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#define NVHOST_DBG_GPU_IOCTL_MAGIC 'D'
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/*
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* /dev/nvhost-dbg-* devices
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*
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* Opening a '/dev/nvhost-dbg-<module_name>' device node creates a new debugger
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* session. nvhost channels (for the same module) can then be bound to such a
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* session.
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*
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* Once a nvhost channel has been bound to a debugger session it cannot be
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* bound to another.
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*
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* As long as there is an open device file to the session, or any bound
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* nvhost channels it will be valid. Once all references to the session
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* are removed the session is deleted.
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*
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*/
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/*
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* Binding/attaching a debugger session to an nvhost gpu channel
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*
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* The 'channel_fd' given here is the fd used to allocate the
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* gpu channel context. To detach/unbind the debugger session
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* use a channel_fd of -1.
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*
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*/
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struct nvhost_dbg_gpu_bind_channel_args {
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__u32 channel_fd; /* in */
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__u32 _pad0[1];
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};
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#define NVHOST_DBG_GPU_IOCTL_BIND_CHANNEL \
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_IOWR(NVHOST_DBG_GPU_IOCTL_MAGIC, 1, \
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struct nvhost_dbg_gpu_bind_channel_args)
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/*
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* Register operations
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*/
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/* valid op values */
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#define NVHOST_DBG_GPU_REG_OP_READ_32 (0x00000000)
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#define NVHOST_DBG_GPU_REG_OP_WRITE_32 (0x00000001)
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#define NVHOST_DBG_GPU_REG_OP_READ_64 (0x00000002)
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#define NVHOST_DBG_GPU_REG_OP_WRITE_64 (0x00000003)
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/* note: 8b ops are unsupported */
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#define NVHOST_DBG_GPU_REG_OP_READ_08 (0x00000004)
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#define NVHOST_DBG_GPU_REG_OP_WRITE_08 (0x00000005)
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/* valid type values */
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GLOBAL (0x00000000)
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX (0x00000001)
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX_TPC (0x00000002)
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX_SM (0x00000004)
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX_CROP (0x00000008)
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX_ZROP (0x00000010)
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/*#define NVHOST_DBG_GPU_REG_OP_TYPE_FB (0x00000020)*/
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#define NVHOST_DBG_GPU_REG_OP_TYPE_GR_CTX_QUAD (0x00000040)
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/* valid status values */
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#define NVHOST_DBG_GPU_REG_OP_STATUS_SUCCESS (0x00000000)
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#define NVHOST_DBG_GPU_REG_OP_STATUS_INVALID_OP (0x00000001)
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#define NVHOST_DBG_GPU_REG_OP_STATUS_INVALID_TYPE (0x00000002)
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#define NVHOST_DBG_GPU_REG_OP_STATUS_INVALID_OFFSET (0x00000004)
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#define NVHOST_DBG_GPU_REG_OP_STATUS_UNSUPPORTED_OP (0x00000008)
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#define NVHOST_DBG_GPU_REG_OP_STATUS_INVALID_MASK (0x00000010)
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struct nvhost_dbg_gpu_reg_op {
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__u8 op;
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__u8 type;
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__u8 status;
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__u8 quad;
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__u32 group_mask;
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__u32 sub_group_mask;
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__u32 offset;
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__u32 value_lo;
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__u32 value_hi;
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__u32 and_n_mask_lo;
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__u32 and_n_mask_hi;
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};
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struct nvhost_dbg_gpu_exec_reg_ops_args {
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__u64 ops; /* pointer to nvhost_reg_op operations */
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__u32 num_ops;
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__u32 _pad0[1];
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};
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#define NVHOST_DBG_GPU_IOCTL_REG_OPS \
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_IOWR(NVHOST_DBG_GPU_IOCTL_MAGIC, 2, \
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struct nvhost_dbg_gpu_exec_reg_ops_args)
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/* Enable/disable/clear event notifications */
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struct nvhost_dbg_gpu_events_ctrl_args {
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__u32 cmd; /* in */
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__u32 _pad0[1];
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};
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/* valid event ctrl values */
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#define NVHOST_DBG_GPU_EVENTS_CTRL_CMD_DISABLE (0x00000000)
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#define NVHOST_DBG_GPU_EVENTS_CTRL_CMD_ENABLE (0x00000001)
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#define NVHOST_DBG_GPU_EVENTS_CTRL_CMD_CLEAR (0x00000002)
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#define NVHOST_DBG_GPU_IOCTL_EVENTS_CTRL \
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_IOWR(NVHOST_DBG_GPU_IOCTL_MAGIC, 3, \
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struct nvhost_dbg_gpu_events_ctrl_args)
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/* Powergate/Unpowergate control */
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#define NVHOST_DBG_GPU_POWERGATE_MODE_ENABLE 1
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#define NVHOST_DBG_GPU_POWERGATE_MODE_DISABLE 2
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struct nvhost_dbg_gpu_powergate_args {
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__u32 mode;
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};
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#define NVHOST_DBG_GPU_IOCTL_POWERGATE \
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_IOWR(NVHOST_DBG_GPU_IOCTL_MAGIC, 4, \
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struct nvhost_dbg_gpu_powergate_args)
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#define NVHOST_DBG_GPU_IOCTL_LAST \
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_IOC_NR(NVHOST_DBG_GPU_IOCTL_POWERGATE)
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#define NVHOST_DBG_GPU_IOCTL_MAX_ARG_SIZE \
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sizeof(struct nvhost_dbg_gpu_exec_reg_ops_args)
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#endif
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