161 lines
3.7 KiB
C
161 lines
3.7 KiB
C
/*
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* Copyright (c) 2011-2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __TEGRA_SOCTHERM_H
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#define __TEGRA_SOCTHERM_H
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/* This order must match the soc_therm HW register spec */
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enum soctherm_sense {
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TSENSE_CPU0 = 0,
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TSENSE_CPU1,
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TSENSE_CPU2,
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TSENSE_CPU3,
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TSENSE_MEM0,
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TSENSE_MEM1,
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TSENSE_GPU,
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TSENSE_PLLX,
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TSENSE_SIZE,
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};
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/* This order must match the soc_therm HW register spec */
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enum soctherm_therm_id {
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THERM_CPU = 0,
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THERM_GPU,
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THERM_MEM,
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THERM_PLL,
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THERM_SIZE,
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};
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enum soctherm_throttle_id {
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THROTTLE_LIGHT = 0,
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THROTTLE_HEAVY,
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THROTTLE_SIZE,
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};
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enum soctherm_throttle_dev_id {
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THROTTLE_DEV_CPU = 0,
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THROTTLE_DEV_GPU,
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THROTTLE_DEV_SIZE,
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THROTTLE_DEV_NONE,
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};
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struct soctherm_sensor {
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bool sensor_enable;
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bool zone_enable;
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int tall;
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int tiddq;
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int ten_count;
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int tsample;
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int tsamp_ate;
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u8 pdiv;
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u8 pdiv_ate;
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};
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struct soctherm_therm {
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bool zone_enable;
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int passive_delay;
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int num_trips;
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int hotspot_offset;
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struct thermal_trip_info trips[THERMAL_MAX_TRIPS];
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struct thermal_zone_params *tzp;
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};
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struct soctherm_throttle_dev {
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bool enable;
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u8 dividend;
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u8 divisor;
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u16 duration;
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u8 step;
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};
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struct soctherm_throttle {
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u8 priority;
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struct soctherm_throttle_dev devs[THROTTLE_DEV_SIZE];
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};
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struct soctherm_tsensor_pmu_data {
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u8 poweroff_reg_data;
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u8 poweroff_reg_addr;
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u8 controller_type;
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u8 i2c_controller_id;
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u8 pinmux;
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u8 pmu_16bit_ops;
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u8 pmu_i2c_addr;
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};
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struct soctherm_sensor2tsensorcalib {
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int tsensor;
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u32 calib_val;
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};
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struct soctherm_fuse_calib_data {
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u32 fuse_calib_base_cp;
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u32 fuse_calib_base_ft;
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u32 actual_temp_cp;
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u32 actual_temp_ft;
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struct soctherm_sensor2tsensorcalib *tsensor_calib;
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int *fuse_corr_alpha;
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int *fuse_corr_beta;
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};
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struct soctherm_platform_data {
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struct soctherm_sensor sensor_data[TSENSE_SIZE];
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struct soctherm_therm therm[THERM_SIZE];
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struct soctherm_throttle throttle[THROTTLE_SIZE];
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struct soctherm_tsensor_pmu_data *tshut_pmu_trip_data;
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struct soctherm_fuse_calib_data *fuse_calib_data;
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unsigned int thermal_irq;
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void __iomem *soctherm_base;
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void __iomem *pmc_base;
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void __iomem *clk_reset_base;
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struct clk *soctherm_clk;
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struct clk *tsensor_clk;
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unsigned long soctherm_clk_rate;
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unsigned long tsensor_clk_rate;
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bool read_hw_temp;
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};
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int soctherm_parse_pmu_dt(struct platform_device *pdev);
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void soctherm_init_sensor(struct platform_device *pdev,
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const struct soctherm_sensor *sensor);
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void soctherm_init_clk_rate(struct platform_device *pdev,
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unsigned long scotherm_clk_rate,
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unsigned long tsensor_clk_rate);
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void soctherm_add_trip_points(struct platform_device *pdev,
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struct thermal_trip_info *trips,
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int *num_trips,
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struct tegra_cooling_device *cdev_data);
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#ifdef CONFIG_ARCH_TEGRA_114_SOC
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int tegra114_soctherm_init(struct device_node *soctherm_dn);
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#else
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static inline int tegra114_soctherm_init(struct device_node *soctherm_dn)
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{ return 0; }
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#endif
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#ifdef CONFIG_ARCH_TEGRA_124_SOC
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int tegra124_soctherm_init(struct device_node *soctherm_dn);
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#else
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static inline int tegra124_soctherm_init(struct device_node *soctherm_dn)
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{ return 0; }
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#endif
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#endif /* __TEGRA_SOCTHERM_H */
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