/* * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. * * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. * * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ /* * Function naming determines intended use: * * _r(void) : Returns the offset for register . * * _o(void) : Returns the offset for element . * * _w(void) : Returns the word offset for word (4 byte) element . * * __s(void) : Returns size of field of register in bits. * * __f(u32 v) : Returns a value based on 'v' which has been shifted * and masked to place it at field of register . This value * can be |'d with others to produce a full register value for * register . * * __m(void) : Returns a mask for field of register . This * value can be ~'d and then &'d to clear the value of field for * register . * * ___f(void) : Returns the constant value after being shifted * to place it at field of register . This value can be |'d * with others to produce a full register value for . * * __v(u32 r) : Returns the value of field from a full register * value 'r' after being shifted to place its LSB at bit 0. * This value is suitable for direct comparison with other unshifted * values appropriate for use in field of register . * * ___v(void) : Returns the constant value for defined for * field of register . This value is suitable for direct * comparison with unshifted values appropriate for use in field * of register . */ #ifndef _hw_host1x04_channel_h_ #define _hw_host1x04_channel_h_ static inline u32 host1x_channel_fifostat_r(void) { return 0x0; } static inline u32 host1x_channel_fifostat_cfempty_v(u32 r) { return (r >> 11) & 0x1; } static inline u32 host1x_channel_fifostat_outfentries_v(u32 r) { return (r >> 24) & 0x1f; } static inline u32 host1x_channel_inddata_r(void) { return 0xc; } static inline u32 host1x_channel_dmastart_r(void) { return 0x14; } static inline u32 host1x_channel_dmaput_r(void) { return 0x18; } static inline u32 host1x_channel_dmaget_r(void) { return 0x1c; } static inline u32 host1x_channel_dmaend_r(void) { return 0x20; } static inline u32 host1x_channel_dmactrl_r(void) { return 0x24; } static inline u32 host1x_channel_dmactrl_dmastop_f(u32 v) { return (v & 0x1) << 0; } static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r) { return (r >> 0) & 0x1; } static inline u32 host1x_channel_dmactrl_dmagetrst_f(u32 v) { return (v & 0x1) << 1; } static inline u32 host1x_channel_dmactrl_dmainitget_f(u32 v) { return (v & 0x1) << 2; } static inline u32 host1x_channel_channelctrl_r(void) { return 0x98; } static inline u32 host1x_channel_stallcount_hi_r(void) { return 0xa4; } static inline u32 host1x_channel_stallcount_lo_r(void) { return 0xa8; } static inline u32 host1x_channel_stallctrl_r(void) { return 0xa0; } static inline u32 host1x_channel_tickcount_hi_r(void) { return 0x90; } static inline u32 host1x_channel_tickcount_lo_r(void) { return 0x94; } static inline u32 host1x_channel_xfercount_hi_r(void) { return 0xb0; } static inline u32 host1x_channel_xfercount_lo_r(void) { return 0xb4; } static inline u32 host1x_channel_xferctrl_r(void) { return 0xac; } #endif