#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"
#include "tegra124-cvb.dtsi"
#include "tegra124-dfll.dtsi"
#include "tegra124-throttle.dtsi"

#include <dt-bindings/memory/tegra-swgroup.h>

/ {
	#address-cells = <2>;
	#size-cells = <1>;

	compatible = "nvidia,tegra124";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
	};

	host1x@50000000 {
		compatible = "nvidia,tegra124-host1x", "simple-bus";
		reg = <0x0 0x50000000 0x00034000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,	/* mpcore syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;	/* mpcore general */
		clocks = <&tegra_car TEGRA124_CLK_HOST1X>,
			 <&tegra_car TEGRA124_CLK_ACTMON>;
		clock-names = "host1x", "actmon";
		iommus = <&smmu
			TEGRA_SWGROUP_MULT_CELLS(TEGRA_SWGROUP_BIT(EPP) |
				TEGRA_SWGROUP_BIT(HC))>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x0 0x54000000 0x0c000000>;

		dc@54200000 {
			compatible = "nvidia,tegra124-dc";
			reg = <0x54200000 0x00040000>,
			      <0x54540000 0x00040000>,
			      <0x545c0000 0x00040000>;
			reg-names = "dc", "sor", "dpaux";
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dc", "dp";
			clocks = <&tegra_car TEGRA124_CLK_DISP1>,
				 <&tegra_car TEGRA124_CLK_PLL_P>,
				 <&tegra_car TEGRA124_CLK_DISP1_EMC>,
				 <&tegra_car TEGRA124_CLK_SOR0>,
				 <&tegra_car TEGRA124_CLK_CLK_M>,
				 <&tegra_car TEGRA124_CLK_PLL_DP>,
				 <&tegra_car TEGRA124_CLK_DPAUX>;
			clock-names = "dc", "parent", "emc", "sor0", "clk_m", "pll_dp", "dpaux";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(DC)>;
			resets = <&tegra_car TEGRA124_CLK_DISP1>;
			reset-names = "dc";
			nvidia,head = <0>;
		};

		dc@54240000 {
			compatible = "nvidia,tegra124-dc";
			reg = <0x54240000 0x00040000>,
			      <0x54280000 0x00040000>;
			reg-names = "dc", "hdmi";
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "dc";
			clocks = <&tegra_car TEGRA124_CLK_DISP2>,
				 <&tegra_car TEGRA124_CLK_PLL_P>,
				 <&tegra_car TEGRA124_CLK_DISP2_EMC>,
				 <&tegra_car TEGRA124_CLK_HDMI>;
			clock-names = "dc", "parent", "emc", "hdmi";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(DCB)>;
			resets = <&tegra_car TEGRA124_CLK_DISP2>;
			reset-names = "dc";
			nvidia,head = <1>;
		};

		sor@54540000 {
			compatible = "nvidia,tegra124-sor";
			reg = <0x54540000 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_SOR0>,
				 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>,
				 <&tegra_car TEGRA124_CLK_PLL_DP>,
				 <&tegra_car TEGRA124_CLK_CLK_M>;
			clock-names = "sor", "parent", "dp", "safe";
			resets = <&tegra_car TEGRA124_CLK_SOR0>;
			reset-names = "sor";
			status = "disabled";
		};

		hdmi@54280000 {
			compatible = "nvidia,tegra114-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_HDMI>,
			       <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
			clock-names = "hdmi", "parent";
			resets = <&tegra_car TEGRA124_CLK_HDMI>;
			reset-names = "hdmi";
			nvidia,hpd-gpio =
				<&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
		};

		dpaux@545c0000 {
			compatible = "nvidia,tegra124-dpaux";
			reg = <0x545c0000 0x00040000>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_DPAUX>,
			       <&tegra_car TEGRA124_CLK_PLL_DP>;
			clock-names = "dpaux", "parent";
			resets = <&tegra_car TEGRA124_CLK_DPAUX>;
			reset-names = "dpaux";
			status = "disabled";
		};

		vic@54340000 {
			compatible = "nvidia,tegra124-vic";
			reg = <0x54340000 0x00040000>;
			clocks = <&tegra_car TEGRA124_CLK_VIC03>,
				 <&tegra_car TEGRA124_CLK_VIC03_EMC>,
				 <&tegra_car TEGRA124_CLK_VIC03_CBUS>;
			clock-names = "vic03", "emc", "cbus";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(VIC)>;
		};

		msenc@544c0000 {
			compatible = "nvidia,tegra124-msenc";
			reg = <0x544c0000 0x00040000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_MSENC>,
				 <&tegra_car TEGRA124_CLK_MSENC_EMC>,
				 <&tegra_car TEGRA124_CLK_MSENC_CBUS>;
			clock-names = "msenc", "emc", "cbus";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(MSENC)>;
		};

		tsec@54500000 {
			compatible = "nvidia,tegra124-tsec";
			reg = <0x54500000 0x00040000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_TSEC>,
				 <&tegra_car TEGRA124_CLK_TSEC_EMC>,
				 <&tegra_car TEGRA124_CLK_TSEC_CBUS>;
			clock-names = "tsec", "emc", "cbus";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(TSEC)>;
		};

		/*
		 * Host1x driver registers ispb device, so we don't
		 * define ispb here.
		 */
		isp@54600000 {
			compatible = "nvidia,tegra124-isp";
			reg = <0x54600000 0x00040000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_ISP>,
				 <&tegra_car TEGRA124_CLK_ISPA_EMC>;
			clock-names = "isp", "emc";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(ISP)
					TEGRA_SWGROUP_CELLS(ISP2B)>;
		};

		gk20a@57000000 {
			compatible = "nvidia,tegra124-gk20a";
			reg = <0x57000000 0x01000000	/* BAR0 */
			       0x58000000 0x01000000>;	/* BAR1 */
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,	/* INT_GPU */
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;	/* INT_GPU_NONSTALL */
			clocks = <&tegra_car TEGRA124_CLK_GPU>,
				 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>,
				 <&tegra_car TEGRA124_CLK_GK20A_EMC>;
			clock-names = "gpu", "pwr", "emc";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(GPUB)>;
		};

		nvavp {
			compatible = "nvidia,tegra124-nvavp";
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA124_CLK_VDE>,
				   <&tegra_car TEGRA124_CLK_AVP_SCLK>,
				   <&tegra_car TEGRA124_CLK_BSEV>,
				   <&tegra_car TEGRA124_CLK_AVP_EMC>,
				   <&tegra_car TEGRA124_CLK_COP>,
				   <&tegra_car TEGRA124_CLK_BSEA>,
				   <&tegra_car TEGRA124_CLK_VCP>;
			clock-names = "vde", "avp.sclk", "bsev", "avp.emc",
					"cop", "bsea", "vcp";
			nvidia,use-smmu;
			nvidia,use-nvavp-audio;
			iommus = <&smmu TEGRA_SWGROUP_MULT_CELLS(TEGRA_SWGROUP_BIT(AVPC) |
					TEGRA_SWGROUP_BIT(A9AVP) | TEGRA_SWGROUP_BIT(VDE))>;
		};

		nvmap {
			compatible = "nvidia,tegra124-nvmap";
			iommus = <&smmu TEGRA_SWGROUP_CELLS(HC)>;
		};
	};

	gic: interrupt-controller@50041000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x0 0x50041000 0x1000>,
		      <0x0 0x50042000 0x1000>,
		      <0x0 0x50044000 0x2000>,
		      <0x0 0x50046000 0x2000>;
		interrupts = <GIC_PPI 9
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer",
			     "nvidia,tegra20-timer";
		reg = <0x0 0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_TIMER>;
		nvidia,pmc = <&pmc>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra124-car", "syscon";
		reg = <0x0 0x60006000 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	apbdma: dma@60020000 {
		compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
		reg = <0x0 0x60020000 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_APBDMA>;
		iommus = <&smmu TEGRA_SWGROUP_CELLS(PPCS)
				TEGRA_SWGROUP_CELLS(PPCS1)>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra124-ahb", "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
		reg = <0x0 0x6000c004 0x14c>;
	};

	gpio: gpio {
		compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
		reg = <0x0 0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra124-pinmux";
		reg = <0x0 0x70000868 0x148>,   /* Pad control registers */
		      <0x0 0x70003000 0x40c>;   /* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 8>;
		status = "disabled";
		clocks = <&tegra_car TEGRA124_CLK_UARTA>;
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 9>;
		status = "disabled";
		clocks = <&tegra_car TEGRA124_CLK_UARTB>;
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006200 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 10>;
		status = "disabled";
		clocks = <&tegra_car TEGRA124_CLK_UARTC>;
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
		reg = <0x0 0x70006300 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 19>;
		status = "disabled";
		clocks = <&tegra_car TEGRA124_CLK_UARTD>;
	};

	pwm: pwm {
		compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
		reg = <0x0 0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car TEGRA124_CLK_PWM>;
		status = "disabled";
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C1>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C2>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C3>;
		clock-names = "div-clk";
		status = "disabled";
	};

	hdmi_ddc: i2c@7000c700 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x7000c700 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C4>;
		clock-names = "div-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
		reg = <0x0 0x7000d000 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_I2C5>;
		clock-names = "div-clk";
		status = "disabled";
	};

	spi0: spi@7000d400 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d400 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC1>;
		clock-names = "spi";
		status = "disabled";
	};

	spi1: spi@7000d600 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d600 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC2>;
		clock-names = "spi";
		status = "disabled";
	};

	spi2: spi@7000d800 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000d800 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC3>;
		clock-names = "spi";
		status = "disabled";
	};

	spi3: spi@7000da00 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000da00 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC4>;
		clock-names = "spi";
		status = "disabled";
	};

	spi4: spi@7000dc00 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000dc00 0x200>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC5>;
		clock-names = "spi";
		status = "disabled";
	};

	spi5: spi@7000de00 {
		compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
		reg = <0x0 0x7000de00 0x200>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA124_CLK_SBC6>;
		clock-names = "spi";
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
		reg = <0x0 0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_RTC>;
		status = "disabled";
	};

	pmc: pmc {
		compatible = "nvidia,tegra124-pmc", "nvidia,tegra114-pmc",
			     "syscon";
		reg = <0x0 0x7000e400 0x800>;
		clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	fuse@7000f800 {
		compatible = "nvidia,tegra124-efuse";
		reg = <0x0 0x7000f800 0x400>,
		      <0x0 0x70000000 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_FUSE>;
	};

	kfuse@7000fc00 {
		compatible = "nvidia,tegra-kfuse";
		reg = <0x0 0x7000fc00 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_KFUSE>;
		clock-names = "kfuse";
	};

	mc: memory-controller@70019000 {
		compatible = "nvidia,tegra124-mc";
		reg = <0x0 0x70019000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	smmu: iommu {
		compatible = "nvidia,tegra124-smmu", "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
		reg = <0x0 0x70019000 0x1000>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,#asids = <128>;
		dma-window = <0x80000000 0x7ff00000>;
		#iommu-cells = <2>;
		#dma-address-cells = <1>;
	};

	memory-controller@7001b000 {
		compatible = "nvidia,tegra124-emc";
		reg = <0x0 0x7001b000 0x1000>;
		#address-cells = <1>;
		#size-cells = <0>;
		nvidia,mc = <&mc>;
		nvidia,pmc = <&pmc>;
		clocks = <&tegra_car TEGRA124_CLK_EMC>,
			<&tegra_car TEGRA124_CLK_PLL_M>,
			<&tegra_car TEGRA124_CLK_PLL_C>,
			<&tegra_car TEGRA124_CLK_PLL_P>,
			<&tegra_car TEGRA124_CLK_CLK_M>,
			<&tegra_car TEGRA124_CLK_PLL_M_UD>,
			<&tegra_car TEGRA124_CLK_PLL_C2>,
			<&tegra_car TEGRA124_CLK_PLL_C3>,
			<&tegra_car TEGRA124_CLK_PLL_C_UD>,
			<&tegra_car TEGRA124_CLK_OVERRIDE_EMC>;
		clock-names = "emc", "pll_m", "pll_c", "pll_p", "clk_m",
			"pll_m_ud", "pll_c2", "pll_c3", "pll_c_ud",
			"emc_override";
	};

	hda@70030000 {
		compatible = "nvidia,tegra-hda";
		reg = <0x0 0x70030000 0x10000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_HDA>,
		         <&tegra_car TEGRA124_CLK_HDA2HDMI>,
			 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
		clock-names = "hda", "hda2hdmi", "hdacodec_2x";
		status = "disabled";
	};

	sdhci@700b0600 {
		compatible = "nvidia,tegra124-sdhci", "nvidia,tegra114-sdhci";
		reg = <0x0 0x700b0600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC4>;
		status = "disabled";
	};

	ahub {
		compatible = "nvidia,tegra124-ahub";
		reg = <0x0 0x70300000 0x200>,
		      <0x0 0x70300800 0x800>,
		      <0x0 0x70300200 0x600>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>,
			 <&tegra_car TEGRA124_CLK_APBIF>,
			 <&tegra_car TEGRA124_CLK_I2S0>,
			 <&tegra_car TEGRA124_CLK_I2S1>,
			 <&tegra_car TEGRA124_CLK_I2S2>,
			 <&tegra_car TEGRA124_CLK_I2S3>,
			 <&tegra_car TEGRA124_CLK_I2S4>,
			 <&tegra_car TEGRA124_CLK_DAM0>,
			 <&tegra_car TEGRA124_CLK_DAM1>,
			 <&tegra_car TEGRA124_CLK_DAM2>,
			 <&tegra_car TEGRA124_CLK_SPDIF_IN>,
			 <&tegra_car TEGRA124_CLK_AMX>,
			 <&tegra_car TEGRA124_CLK_AMX1>,
			 <&tegra_car TEGRA124_CLK_ADX>,
			 <&tegra_car TEGRA124_CLK_ADX1>,
			 <&tegra_car TEGRA124_CLK_AFC0>,
			 <&tegra_car TEGRA124_CLK_AFC1>,
			 <&tegra_car TEGRA124_CLK_AFC2>,
			 <&tegra_car TEGRA124_CLK_AFC3>,
			 <&tegra_car TEGRA124_CLK_AFC4>,
			 <&tegra_car TEGRA124_CLK_AFC5>,
			 <&tegra_car TEGRA124_CLK_AHUB_EMC>;
		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif_in", "amx", "amx1", "adx", "adx1",
			      "afc0", "afc1", "afc2", "afc3", "afc4", "afc5", "ahub.emc";
		ranges = <0x70301000 0x0 0x70301000 0x500>;
		#address-cells = <1>;
		#size-cells = <1>;

		nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>,
			<&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>,
			<&apbdma 12>, <&apbdma 13>, <&apbdma 14>,
			<&apbdma 29>;

		tegra_i2s0: i2s@70301000 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301000 0x100>;
			clocks = <&tegra_car TEGRA124_CLK_I2S0>;
			nvidia,ahub-cif-ids = <4 4>;
			status = "disabled";
		};

		tegra_i2s1: i2s@70301100 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301100 0x100>;
			clocks = <&tegra_car TEGRA124_CLK_I2S1>;
			nvidia,ahub-cif-ids = <5 5>;
			status = "disabled";
		};

		tegra_i2s2: i2s@70301200 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301200 0x100>;
			clocks = <&tegra_car TEGRA124_CLK_I2S2>;
			nvidia,ahub-cif-ids = <6 6>;
			status = "disabled";
		};

		tegra_i2s3: i2s@70301300 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301300 0x100>;
			clocks = <&tegra_car TEGRA124_CLK_I2S3>;
			nvidia,ahub-cif-ids = <7 7>;
			status = "disabled";
		};

		tegra_i2s4: i2s@70301400 {
			compatible = "nvidia,tegra124-i2s";
			reg = <0x70301400 0x100>;
			clocks = <&tegra_car TEGRA124_CLK_I2S4>;
			nvidia,ahub-cif-ids = <8 8>;
			status = "disabled";
		};
	};

	sdhci@700b0000 {
		compatible = "nvidia,tegra124-sdhci", "nvidia,tegra114-sdhci";
		reg = <0x0 0x700b0000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC1>;
		status = "disabled";
	};

	sdhci@700b0200 {
		compatible = "nvidia,tegra124-sdhci", "nvidia,tegra114-sdhci";
		reg = <0x0 0x700b0200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC2>;
		status = "disabled";
	};

	sdhci@700b0400 {
		compatible = "nvidia,tegra124-sdhci", "nvidia,tegra114-sdhci";
		reg = <0x0 0x700b0400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_SDMMC3>;
		status = "disabled";
	};

	phy1: usb-phy@7d000000 {
		compatible = "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d000000 0x4000>,
		      <0x0 0x7d000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USBD>,
			 <&tegra_car TEGRA124_CLK_PLL_U>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		status = "disabled";
	};

	usb@7d000000 {
		compatible = "nvidia,tegra30-ehci", "usb-ehci";
		reg = <0x0 0x7d000000 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USBD>;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	phy2: usb-phy@7d004000 {
		compatible = "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d004000 0x4000>,
		      <0x0 0x7d000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB2>,
			 <&tegra_car TEGRA124_CLK_PLL_U>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		status = "disabled";
	};

	usb@7d004000 {
		compatible = "nvidia,tegra30-ehci", "usb-ehci";
		reg = <0x0 0x7d004000 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB2>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	phy3: usb-phy@7d008000 {
		compatible = "nvidia,tegra30-usb-phy";
		reg = <0x0 0x7d008000 0x4000>,
		      <0x0 0x7d000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB3>,
			 <&tegra_car TEGRA124_CLK_PLL_U>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "reg", "pll_u", "utmi-pads";
		nvidia,hssync-start-delay = <0>;
		nvidia,idle-wait-delay = <17>;
		nvidia,elastic-limit = <16>;
		nvidia,term-range-adj = <6>;
		nvidia,xcvr-setup = <9>;
		nvidia,xcvr-lsfslew = <0>;
		nvidia,xcvr-lsrslew = <3>;
		nvidia,hssquelch-level = <2>;
		nvidia,hsdiscon-level = <5>;
		nvidia,xcvr-hsslew = <12>;
		status = "disabled";
	};

	usb@7d008000 {
		compatible = "nvidia,tegra30-ehci", "usb-ehci";
		reg = <0x0 0x7d008000 0x4000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA124_CLK_USB3>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	usb@70090000 {
		compatible = "nvidia,tegra124-xhci";
		reg = <0x0 0x70090000 0x8000>,
		      <0x0 0x70098000 0x1000>,
		      <0x0 0x70099000 0x1000>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>,
			 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>,
			 <&tegra_car TEGRA124_CLK_XUSB_EMC>;
		clock-names = "xusb_host", "xusb_falcon_src", "xusb.emc";
		nvidia,xusb-phy = <&xusb_phy>;
		status = "disabled";
	};

	xusb_phy: phy@7009f000 {
		compatible = "nvidia,tegra124-xusb-phy";
		reg = <0x0 0x7009f000 0x1000>,
		      <0x0 0x7d000000 0x4000>;
		interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA124_CLK_XUSB_SS>,
			 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>,
			 <&tegra_car TEGRA124_CLK_PLL_U_480M>,
			 <&tegra_car TEGRA124_CLK_CLK_M>,
			 <&tegra_car TEGRA124_CLK_USBD>;
		clock-names = "xusb_ss", "xusb_ss_src", "pll_u_480M",
			      "clk_m", "pad_clk";
		nvidia,pmc = <&pmc>;
		nvidia,clkrst = <&tegra_car>;
		status = "disabled";
	};

	dfll@70110000 {
		compatible = "nvidia,tegra124-dfll";
		reg = <0x0 0x70110000 0x400>;
		clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
			 <&tegra_car TEGRA124_CLK_DFLL_REF>,
			 <&tegra_car TEGRA124_CLK_I2C5>;
		clock-names = "soc", "ref", "i2c";
		tuning = <&{/cpu_dfll_tuning}>;
		cvb-table = <&{/cpu_dfll_cvb_table}>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	};
};